Nowadays, the use of magnetic layers for micro- and nano-devices gains lots of interest for many applications, such as for example MRAM memories, spin torque oscillators, hard disk read heads and sensor applications, and even magnetic logic circuits. An important problem occurring during processing of such devices is the patterning of the magnetic layers. Magnetic devices typically comprise multilayers of ultrathin magnetic and non-magnetic layers. Reactive etching of such multilayers is difficult, because of the variation in materials, which requires different etchants for different materials. Therefore, the patterning of such multilayer stacks is done typically using Reactive Ion Etching (RIE) or ion milling techniques. A drawback of these techniques is the redeposition of a mixture of all etched materials during patterning of the layers. In case of magnetic layers or conductive layers in general, this redeposition consists of conductive material, causing an electrical shortcut of the etched stack, due to this conductive sidewall deposition, as illustrated in FIGS. 1A and 1B. FIG. 1A illustrates a magnetic stack before ion milling. The magnetic stack 10 comprises two magnetic layers 11, separated by an insulating layer 12, e.g. a thin oxide layer, a conductive, e.g. metal, bottom electrode 13 and a conductive, e.g. metal, top electrode 14. When the magnetic stack 10 needs to be patterned, a suitably patterned resist layer 15 is provided. FIG. 1B illustrates the magnetic stack 10 after ion milling. It can be seen that during ion milling a conductive polymer 16 is deposited at the sidewalls of the resist 15, the magnetic layers 11 and the insulating layer 12. As the sidewalls of the magnetic layers 11 and the insulating layer 12 are covered with this conductive polymer 16, the magnetic layers 11 are short-circuited. Obviously, this unwanted electrical shortcut will lead to complete malfunctioning of the final device.
A second problem during fabrication of such magnetic devices with small dimensions, e.g. in the nanometer range, is the alignment of the metallization to realize electrical contact with the patterned device. The conventional way (patterning of the stack 10—see FIG. 2A, oxide 20 deposition—see FIG. 2B, photoresist 21 deposition—see FIG. 2C, contact hole formation by litho and oxide 20 etch—see FIGS. 2D and 2E, and contact hole filling with metal) cannot be used, due to the very high resolution and alignment requirements for the lithographic patterning step. As can be seen from FIG. 2D, standard litho may have a limited resolution and an extreme good alignment, leading to a wrong electrical contact. In alternative embodiments, see FIG. 2E, standard litho may have an extreme good resolution but a considerable alignment error, which again leads to a wrong electrical contact. Insufficient resolution or inaccurate alignment will result again in a conductive shortcut of the devices, resulting again in complete malfunctioning of the final device (see FIGS. 2D, and 2E). Only very advanced litho has both an extreme good resolution and alignment, see FIG. 2F, which yields a correct electrical contact. However, very advanced litho puts a lot of severe constraints on the tools used and is not always available. Hence alternative approaches for this metallization step should be used.
An interesting process sequence for self-aligned electrical contact to a nanomagnetic device is illustrated in FIG. 3A to 3F. The sequence starts from a patterned magnetic stack 10 as for example illustrated in FIG. 3A, and comprises the use of insulating material, e.g. oxide 30 deposition—see FIG. 3B, followed by CMP—FIG. 3C, to create an insulating layer surrounding the magnetic devices. The insulating material CMP is applied to free the top metal electrode 14. The timing of the CMP is very critical, especially when the metal layer of the top electrode 14 is thin (and a thicker metal layer results in more sidewall deposition as illustrated with respect to FIG. 1B). After this CMP process step 31, a metal layer 32 is deposited, which is patterned by lithography and etch. In the latter case, the litho step is not critical: large metal patterns can be made, and alignment is not critical, since the underlying magnetic device is completely surrounded by insulating oxide (see FIGS. 3D, 3E, and 3F). Important issue however is the oxide CMP 31 process. Not only the selectivity of the CMP process towards the various exposed materials should be optimized, but especially the timing if this CMP process is critical: over-polishing (CMP time too long) leads to either a removal of insulation around the device, so that sidewalls of magnetic layers 11 are not covered with insulation anymore, resulting again in a shortcut, or to removal of the top part device itself which in both case would lead to complete malfunctioning devices—see FIG. 3F. If the CMP step is too short, as illustrated in FIG. 3D, the top metal electrode 14 is still covered with insulating material 30 when the CMP stops, preventing any electrical contact of the metal layer 32 with the magnetic device. Hence no functional device is obtained. To obtain a successful CMP process, not only the CMP timing has to be perfect, as illustrated in FIG. 3E, but also the top metal electrode 14 has to be thick enough, leading to a more problematic patterning and redeposition problem.
One method used in the state of the art to solve the redeposition issue is the step of removing the redeposition after the patterning step using a second etching step by putting the wafer under an angle to the ion beam ‘skewed ion beam etching’. The disadvantage of this method is that skewed etching is a rather complex experimental technique not transferable to standard CMOS processing. Moreover there is still the issue of alignment and need for a controlled CMP process.
US20070166840 (US'840) describes a method for forming magnetic tunnel junctions in integrated circuits wherein sidewall spacer features are formed during the processing of the film stack. These sidewall spacer features create a tapered masking feature which helps to avoid byproduct redeposition during the etching of the film stack. However the disadvantage of this method is that the requirements for patterning (need for advanced lithographic techniques to realize alignment of top contact) remains and the fact that the spacers create a significant increase in dimensions.
US'840 discloses a method to solve the problem of redeposition but does not solve the alignment problem. Furthermore US'840 requires much smaller photoresist mask dimensions and results in a much weaker CD (critical Dimension) control.
Hence there still exists a problem to pattern a stack of magnetic layers thereby eliminating the above mentioned alignment problems thereby avoiding the need of very advanced lithography. Furthermore it is still desirable to facilitate the above mentioned oxide CMP process drastically such that the timing of the oxide CMP process is easier to control and without the risk of damaging the device or the surrounding insulating layer.